The present invention is directed to metal oxide semiconductor (MOS) devices such as metal oxide semiconductor capacitors (MOSCAPs), complementary metal oxide semiconductor (CMOS) field effect transistors (FETs) and bipolar transistors such as lateral pnp devices, and in particular to an improved design for MOS devices which enhances the reliability of the same. The MOS devices of the present invention have improved reliability since substantially little or no oxide breakdown at the Rx corner or edge occurs during device biasing.
A major factor that inhibits prior art MOS devices such as MOSCAPs is the overlap of the gate polysilicon and the Rx edge of the semiconducting substrate. The term xe2x80x9cRx edgexe2x80x9d is used herein to denote the area of the semiconducting material which is bounded by the shallow trench isolation (STI) region. A typical prior art MOSCAP structure is shown in FIGS. 1(a)-(b). Specifically, FIG. 1(a) is a top view of a prior art MOSCAP structure, whereas FIG. 1(b) is a cross-sectional view of the same structure. In such structures, the shallow trench isolation (STI) corner or Rx edge region (hereinafter referred to as just the Rx edge) becomes an emitter of hot electrons when the base plate becomes negatively biased. These hot electrons degrade the oxide reliability.
The above overlap problem is not something that can be typically avoided since the prior art requires the same for eliminating the possibility of damaging the gate oxide when contacting the gate polysilicon with a metal contact.
For STI designs, the contact problem is alleviated by placing the gate polysilicon over the Rx edge so that the gate can be contacted over the trench oxide. This design, however, results in a less reliable MOSCAP structure due to the high electrical field formed at the Rx edge when the bottom plate of the MOSCAP is biased negative. The resulting device is thus unreliable due to a greater potential for oxide breakdown at the Rx edge.
FIG. 2 shows another prior art MOS device. Specifically, FIG. 2 illustrates a top view of a prior art field effect transistor (FET) design. In this figure, the gate polysilicon also overlaps the Rx edge; therefore the above problem exists for this prior art FET design as well.
In view of the above mentioned drawback with prior art MOS designs, there is a need for a new MOS device which eliminates the overlap of the gate polysilicon with the Rx edge of the device. Such a design would allow for fabricating MOS devices which have a greater reliability than those currently be used.
One object of the present invention is to provide a highly reliable MOS device which eliminates the thin oxide areas over STI corners, i.e. the Rx edge.
Another object of the present invention is to design a MOS device which provides a solution for contacting the gate polysilicon over an Rx structure.
A further object of the present invention is to design a MOS device which has improved series resistance to the doped gate region of the device.
These and other objects and advantages are met by utilizing a MOS device which comprises: a semiconducting substrate; a first doped region formed in said semiconducting substrate; a dielectric region formed on said first doped region, wherein said dielectric region has a substantially thicker portion comprising a nitride pad formed over a screen oxide layer; a gate region formed over said dielectric region, said gate region being doped with a n- or p-type dopant; and an electrical contact connected directly to said gate region over the substantially thicker portion of said dielectric region.
The term xe2x80x9cMOS devicexe2x80x9d is used herein to denote MOSCAP devices, FET devices, bipolar transistors such as lateral pnp devices as well as other MOS devices which contain a gate region for controlling the device.
Another aspect of the present invention relates to a method of fabricating the above described MOS devices. Specifically, the method of the present invention comprises the steps of:
(a) providing a MOS structure, said structure comprising a semiconducting substrate having a screen oxide formed on a portion of said semiconducting substrate;
(b) implanting a first impurity region in said semiconducting substrate using said screen oxide as an implantation mask;
(c) forming a nitride pad on said screen oxide;
(d) removing portions of said nitride pad and said screen oxide, but leaving a stack region of said nitride pad and said screen oxide on said semiconducting substrate;
(e) forming a dielectric layer abutting said stack region so as to form a dielectric region having a substantially thicker portion;
(f) forming a gate region over said dielectric region;
(g) patterning said gate region and said dielectric region so as to provide a structure having said gate region over said substantially thicker portion of said dielectric region;
(h) doping said patterned gate region with a n- or p-type dopant; and
(i) forming metal contacts on said doped gate region over said substantially thicker portion and over said first doped region.
In one embodiment of the invention, step (h) occurs before the patterning step, i.e. between steps (f) and (g).